1. Field of Invention
The present invention relates to an integrated circuit (IC) fabrication, and particularly to a measurement method of an overlay mark for checking the alignment accuracy between layers on a wafer.
2. Description of Related Art
As the level of integration of integrated circuits is increased, the demand for increasing the feature density or reducing the pitch size becomes the mainstream in the semiconductor industry, and the key technology is in photolithography. In the photolithography module, the patterns are transferred from a photomask to a wafer, so that the accuracy in the pattern transferring process is quite important. Therefore, an overlay mark is generally formed on a wafer to check the alignment accuracy between layers.
The existing overlay measurement is an optical image based measurement. The accuracy of the measurement is usually affected by processes including chemical mechanical polishing (CMP), etching, gap fill, film topography, etc. However, it has been difficult to prove the overlay measurement results.